View P320DT70RI_3353011.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

publication number 24075 revision c amendment +3 issue date june 13, 2005 am29pl320d data sheet retired product this product has been retired and is not recommended for designs. for new and current designs, s29gl032m supersedes am29pl320d and is the factory-recommended migration path. please refer to the s29gl032m datasheet for specifications and ordering information. availability of this docu- ment is retained for reference and historical purposes only. june 2005 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these produc ts will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions.
this page left intentionally blank.
publication# 24075 rev: c amendment/ +3 issue date: june 13, 2005 refer to amd?s website (www.amd.com/flash) for the latest information. am29pl320d 32 megabit (2 m x 16-bit/1 m x 32-bit) cmos 3.0 volt-only high performance page mode flash memory distinctive characteristics architectural advantages 32 mbit page mode device ? word (16-bit) or double word (32-bit) mode selectable via word# input ? page size of 8 words/4 double words: fast page read access from random locations within the page single power supply operation ? full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications ? regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors flexible sector architecture ? sector sizes (x16 configuration): one 16 kword, two 8 kword, one 96 kword and fifteen 128 kword sectors ? supports full chip erase secsi ? (secured silicon) sector region ? current version of device has 512 words (256 double words); future versions will have 128 words (64 double words) top or bottom boot block configuration manufactured on 0.23 m process technology 20-year data retention at 125 c minimum 1 million erase cycles guarantee per sector performance characteristics high performance read access times ? page access times as fast as 20 ns ? random access times as fast as 60 ns power consumption (typical values) ? initial page read current: 4 ma (1 mhz), 40 ma (10 mhz) ? intra-page read current: 15 ma (10 mhz), 50 ma (33 mhz) ? program/erase current: 25 ma ? standby mode current: 2 a software features software command-set comp atible with jedec standard ? backward compatible with am29f and am29lv families cfi (common flash in terface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation hardware features sector protection ? a hardware method of locking a sector to prevent any program or erase operations within that sector ? sectors can be locked via programming equipment ? temporary sector unprotect command sequence allows code changes in previously locked sectors acc (acceleration) input provides faster programming times wp# (write protect) input ?at v il , protects the first or last 32 kword sector, regardless of sector protect/unprotect status ?at v ih , allows removal of sector protection ? an internal pull up to v cc is provided package options ? 84-ball fbga this product has been retired and is not recommended for designs. for new and current designs, s29gl032m supersedes am29pl320d and is the factory-recommended migration path. please refer to the s29gl032m datasheet for specifications and ordering information. availability of this document is retained for reference and historical purposes only.
2 am29pl320d june 13, 2005 general description the am29pl320d is a 32 mbit, 3.0 volt-only page mode flash memory device organized as 2,097,152 words or 1,048,576 double words. the device is of- fered in an 84-ball fbga package. the word-wide data (x16) appears on dq15?dq0; the double word- wide (x32) data appears on dq31?dq0. the device is available in both top and bottom boot versions. this device can be programmed in-system or with in stan- dard eprom programmers. a 12.0 v v pp or 5.0 v cc are not required for write or erase operations. the device offers fast page access times of 20, 25, and 35 ns, with corresponding random access times of 60, 70, 90 ns, respectively, allowing high speed micro- processors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#), and output enable (oe#) controls. page mode features the device is ac timing, input, output, and package compatible with 16 mbit x 16 page mode mask rom . the page size is 8 words or 4 double words. after initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. standard flash memory features the device requires only a single 3.0 volt power sup- ply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. write cy- cles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm?an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase com- mand sequence. this initiates the embedded erase algorithm?an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. the secsi ? sector (secured silicon) is an extra sec- tor capable of being permanently locked by amd or customers. the secsi indicator bit (dq7) is perma- nently set to a 1 if the part is factory locked , and set to a 0 if customer lockable . this way, customer lock- able parts can never be used to replace a factory locked part. current version of device has 512 words (256 double words); future versions will have only 128 words (64 double words). this should be considered during system design. fac- tory locked parts can store a secure, random 16 byte esn (electronic serial number), customer code (pro- grammed through amd?s expressflash service), or both. customer lockable parts may be programmed after being shipped from amd. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection.
june 13, 2005 am29pl320d 3 table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 input configuration . . . . . . . . . . . . . . . . . . . . . . . . 7 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . 8 standard products .................................................................... 8 device bus operations . . . . . . . . . . . . . . . . . . . . . . 9 table 1. am29pl320d device bus operations ................................9 word/double word configuration ............................................. 9 requirements for reading array data ..................................... 9 read mode ............................................................................... 9 random read (non-page mode read) ............................................9 page mode read .................................................................... 10 table 2. double word mode ...........................................................10 table 3. word mode ........................................................................10 writing commands/command sequences ............................ 11 accelerated program operation ......................................................11 program and erase operation status .................................... 11 standby mode ........................................................................ 11 automatic sleep mode ........................................................... 11 output disable mode .............................................................. 11 table 4. sector address table, top boot (am29pl320dt) ...........12 table 5. secsi ? sector addresses for top boot devices .............12 table 6. sector address table, bottom boot (am29pl320db) ......13 table 7. secsi ? sector addresses for bottom boot devices .......................................................................13 autoselect mode ..................................................................... 14 table 8. am29pl320d autoselect codes (high voltage method) ..14 sector protection/unprotection ............................................... 14 common flash memory interface (cfi) . . . . . . . 15 table 9. cfi query identification string ..........................................15 table 10. system interface string ...................................................16 table 11. device geometry definition ............................................16 table 12. primary vendor-specific extended query ......................17 secsi ? (secured silicon) sector flash memory region ....... 18 factory locked: secsi sector programmed and protected at the factory .................................................................18 customer lockable: secsi sector not programmed or locked at the factory .................................................................................18 figure 1. secsi sector protect verify.............................................. 19 write protect (wp#) ................................................................ 19 hardware data protection ...................................................... 19 low v cc write inhibit ......................................................................19 write pulse ?glitch? protection ........................................................19 logical inhibit ..................................................................................19 power-up write inhibit ....................................................................19 command definitions . . . . . . . . . . . . . . . . . . . . . . 19 reading array data ................................................................ 19 reset command ..................................................................... 20 autoselect command sequence ............................................ 20 enter secsi ? sector/exit secsi sector command sequence .............................................................. 20 word/double word program command sequence ............... 20 unlock bypass command sequence ..............................................21 figure 2. program operation .......................................................... 21 chip erase command sequence ........................................... 22 sector erase command sequence ........................................ 22 erase suspend/erase resume commands ........................... 22 figure 3. erase operation.............................................................. 23 temporary sector unpr otect enable/disable command sequence .............................................................. 24 figure 4. temporary sector unprotect algorithm .......................... 24 command definitions ............................................................. 25 table 13. command definitions (double word mode) .................. 25 table 14. command definitions (word mode) ............................... 26 write operation status . . . . . . . . . . . . . . . . . . . . . 27 dq7: data# polling ................................................................. 27 figure 5. data# polling algorithm .................................................. 27 dq6: toggle bit ...................................................................... 28 dq2: toggle bit ...................................................................... 28 reading toggle bits dq6/dq2 ............................................... 28 dq5: exceeded timing limits ................................................ 28 figure 6. toggle bit algorithm........................................................ 29 dq3: sector erase timer ....................................................... 29 table 15. write operation status ................................................... 30 absolute maximum ratings. . . . . . . . . . . . . . . . . 31 figure 7. maximum negative overshoot waveform ...................... 31 figure 8. maximum positive overshoot waveform........................ 31 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 31 commercial (c) devices ......................................................... 31 industrial (i) devices ............................................................... 31 v cc supply voltages .............................................................. 31 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 cmos compatible .................................................................. 32 zero power flash ................................................................... 33 figure 9. i cc1 current vs. time (showing active and automatic sleep currents) ........................................................................................ 33 figure 10. typical i cc1 vs. frequency ........................................... 33 figure 11. test setup..................................................................... 34 table 16. test specifications ......................................................... 34 key to switching waveforms. . . . . . . . . . . . . . . . 34 figure 12. input waveforms and measurement levels ................. 34 read operations .................................................................... 35 figure 13. conventional read operations timings ....................... 36 figure 14. page read timings ...................................................... 36 double word/word configuration (word#) ........................ 37 figure 15. word# timings for read operations.......................... 37 figure 16. word# timings for write operations.......................... 37 program/erase operations .................................................... 38 figure 17. program operation timings.......................................... 39 figure 18. ac waveforms for chip/sector erase operations........ 40 figure 19. data# polling timings (during embedded algorithms). 40 figure 20. toggle bit timings (during embedded algorithms)...... 41 figure 21. dq2 vs. dq6 for erase and erase suspend operations ............................................................ 41 alternate ce# controlled erase/program operations ..................................................... 42 figure 22. alternate ce# controlled write operation timings ...... 43 erase and programming performance . . . . . . . 44 latchup characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 bga package capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 46 fbf084?84-ball fine pitch ball grid array (fbga) 11 x 12 mm ..... 46 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 47 revision a (march 7, 2001) .................................................... 47
4 am29pl320d june 13, 2005 revision b (june 12, 2001) .................................................... 47 revision b+1 (august 30, 2001) ............................................. 47 revision c (october 22, 2002) ............................................... 47 revision c+1 (july 21, 2003) ................................................. 47 revision c+2 (october 2, 2003) ............................................. 47
june 13, 2005 am29pl320d 5 product selector guide note: see ?ac characteristics? for full specifications. block diagram family part number am29pl320d speed option regulated voltage range: v cc =3.0?3.6 v 60r 70r full voltage range: v cc = 2.7?3.6 v 70 90 max access time, ns (t acc )607090 max ce# access time, ns (t ce )607090 max page access time, ns (t pac c )202530 max oe# access time, ns (t oe )202530 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# word# acc wp# ce# oe# stb stb dq31 ? dq0 data latch y-gating cell matrix address latch a19?a0 a1, a0, a-1
6 am29pl320d june 13, 2005 connection diagrams special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. c1 d1 e1 f1 g1 h1 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq8 a15 nc nc dq31/a-1 nc nc we# nc nc nc nc nc wp# acc nc a12 a11 nc dq2 a0 a3 a2 a1 dq21 a8 dq5 dq18 dq16 dq0 a5 a4 dq6 dq7 dq4 dq19 v ss dq1 v cc v ss v cc dq20 j1 j2 k2 j3 k3 j4 k4 j5 k5 j6 k6 a14 a13 nc nc a9 a10 a7 b7 c7 d7 e7 f7 g7 h7 a8 b8 c8 d8 e8 f8 g8 h8 v ss dq24 dq11 dq28 dq29 dq15 v ss ce# dq25 a18 dq10 v ss dq14 oe# word# nc j7 k7 j8 k8 v cc a19 a17 a16 b9 c9 d9 e9 f9 g9 h9 dq26 v cc dq27 dq12 dq13 v cc dq30 j9 dq9 a6 a7 dq23 v ss dq22 dq3 v cc dq17 84-ball fbga top view, balls facing down
june 13, 2005 am29pl320d 7 input configuration a19?a0 = 20 address inputs dq30?dq0 = 31 data inputs/outputs dq31/a-1 = in double word mode, functions as dq31. in word mode, functions as a-1 (lsb address input) word# = word enable input when low, enables word mode when high, enables double word mode wp# = hardware write protect input acc = acceleration input ce# = chip enable input oe# = output enable input we# = write enable input v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = input not connected internally logic symbol 20 16 or 32 dq31?dq0 (a-1) a19?a0 ce# oe# we# word# wp# acc
8 am29pl320d june 13, 2005 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combi- nation) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. am29pl320d b 60r wp i temperature range i = industrial (?40 c to +85 c) package type wp = 84-ball fine pitch ball grid array (fbga) 0.8 mm pitch (fbf084) speed option see product selector guide and valid combinations boot code sector architecture t = top boot sector b = bottom boot sector device number/description am29pl320d 32 megabit (2 m x 16-bit/1 m x 32-bit) cmos 3.0 volt-only high performance page mode flash memory valid combinations package marking voltage range am29pl320dt60r, am29pl320db60r wpi p320dt60ri, p320db60ri v cc = 3.0?3.6 v am29pl320dt70r, am29pl320db70r P320DT70RI, p320db70ri am29pl320dt70, am29pl320db70 p320dt70vi, p320db70vi v cc = 2.7?3.6 v am29pl320dt90, am29pl320db90 p320dt90vi, p320db90vi
june 13, 2005 am29pl320d 9 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register it- self does not occupy any addressable memory location. the register is composed of latches that store the commands, along with the address and data infor- mation needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. the following subsections describe each of these operations in further detail. table 1. am29pl320d device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = don?t care, a in = address in, d in = data in, d out = data out notes: 1. addresses are a19?a0 in double word mode (word# = v ih ), a19?a-1 in word mode (word# = v il ). 2. the sector protect and sector unprotect functions must be implemented via programming equipment. see the ?sector protection/unprotection? section. word/double word configuration the word# input controls whether the device data i/os dq31?dq0 operate in the word or double word configuration. if the word# input is set at v ih , the de- vice is in double word configuration; dq31?dq0 are active and controlled by ce# and oe#. if the word# input is set at logic ?0?, the device is in word configuration, and only data i/os dq15?dq0 are active and controlled by ce# and oe#. the data i/os dq30?dq16 are tri-stated, and the dq31 input is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# inputs to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output inputs. we# should remain at v ih . the word# input determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read operations table for timing specifica- tions and to figure 13 for the timing diagram. i cc1 in the dc characteristics table represents the active cur- rent specification for reading array data. read mode random read (non-page mode read) the device has two control functions which must be satisfied in order to obtain data at the outputs. ce# is the power control and should be used for device selec- tion. oe# is the output control and should be used to gate data to the output inputs if the device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad- dresses and stable ce# to valid data at the output inputs. the output enable access time is the delay from the falling edge of oe# to valid data at the output inputs (assuming the addresses have been stable for at least t acc ?t oe time). operation ce# oe# we# wp# addresses (note 1) dq7? dq0 dq31?dq8 word# = v ih word# = v il read l l h x a in d out d out dq30?dq16 = high-z, dq31 = a-1 write l h l x a in d in d in standby v cc 0.3 v x x x x high-z high-z high-z output disable l h h x x high-z high-z high-z
10 am29pl320d june 13, 2005 page mode read the am29pl320d is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the am29pl320d device is 8 words, or 4 dou- ble words, with the appropriate page being selected by the higher address bits a19?a2 and the lsb bits a1? a0 (in the double word mode) and a1 to a-1 (in the word mode) determining the specific word/double word within that page. this is an asynchronous operation with the microprocessor supplying the specific word or double word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pac c . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . here again, ce# selects the device and oe# is the output control and should be used to gate data to the output inputs if the device is selected. fast page mode accesses are obtained by keeping a19?a2 constant and changing a1 to a0 to select the specific double word, or changing a1 to a-1 to select the specific word, within that page. the following tables determine the specific word and double word within the selected page: table 2. double word mode table 3. word mode word a1 a0 double word 0 0 0 double word 1 0 1 double word 2 1 0 double word 3 1 1 word a1 a0 a-1 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1
june 13, 2005 am29pl320d 11 writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the word# input determines whether the device accepts program data in double words or words. refer to ?word/double word configu- ration? for more information. the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word or double word, instead of four. the ?word/double word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 4 indicates the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?command definitions? section has de- tails on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? and ?autoselect command sequence? sections for more information. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ?ac characteristics? section contains timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. if the system asserts v hh (11.5 to 12.5 v) on this in- put, the device automatically enters the aforemen- tioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program opera- tions. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the acc pin returns the device to normal operation. note that the acc pin must not be at v hh for operations other than acceler- ated programming, or device damage may result. in addition, the acc pin must not be left floating or un- connected; inconsistent behavior of the device may re- sult. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to ?write operation status? for more information, and to ?ac characteris- tics? for timing diagrams. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# input is both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# is held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. note that during automatic sleep mode, oe# must be at v ih before the device reduces cur- rent to the stated sleep mode specification. output disable mode when the oe# input is at v ih , output from the device is disabled. the output inputs are placed in the high im- pedance state.
12 am29pl320d june 13, 2005 table 4. sector address table, top boot (am29pl320dt) note: address range is a19?a-1 if device is in word mode (word# = v il ). address range is a19?a0 if device is in double word mode (word# = v ih ). table 5. secsi ? sector addresses for top boot devices sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kwords/ kdouble words) address range (in hexadecimal) word mode (x16) double word mode (x32) sa0 0000 xxxx 128/64 000000?01ffff 00000?0ffff sa1 0001 xxxx 128/64 020000?03ffff 10000?1ffff sa2 0010 xxxx 128/64 040000?05ffff 20000?2ffff sa3 0011 xxxx 128/64 060000?07ffff 30000?3ffff sa4 0100 xxxx 128/64 080000?09ffff 40000?4ffff sa5 0101 xxxx 128/64 0a0000?0bffff 50000?5ffff sa6 0110 xxxx 128/64 0c0000?0dffff 60000?6ffff sa7 0111 xxxx 128/64 0e0000?0fffff 70000?7ffff sa8 1000 xxxx 128/64 100000?11ffff 80000?8ffff sa9 1001 xxxx 128/64 120000?13ffff 90000?9ffff sa101010 xxxx 128/64 140000?15ffff a0000?affff sa111011 xxxx 128/64 160000?17ffff b0000?bffff sa121100 xxxx 128/64 180000?19ffff c0000?cffff sa131101 xxxx 128/64 1a0000?1bffff d0000?dffff sa141110 xxxx 128/64 1c0000?1dffff e0000?effff sa151111 0000?1011 96/48 1e0000?1f7fff f0000?fbfff sa1611111100 8/4 1f8000?1f9fff fc000?fcfff sa1711111101 8/4 1fa000?1fbfff fd000?fdfff sa181111111x 16/8 1fc000?1fffff fe000?fffff device sector address a7?a0 sector size (x16) address range (x32) address range am29pl320dt 00000000 512 words/256 double words 000000h?0001ffh 00000h?000ffh
june 13, 2005 am29pl320d 13 table 6. sector address table, bottom boot (am29pl320db) note: address range is a19?a-1 if device is in word mode (word# = v il ). address range is a19?a0 if device is in double word mode (word# = v ih ). table 7. secsi ? sector addresses for bottom boot devices sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kwords/ kdouble words) address range (in hexadecimal) word mode (x16) double word mode (x32) sa0 0 0 0 0 0 0 0 x 16/8 000000?003fff 00000?001ff sa1 0 0 0 0 0 0 1 0 8/4 004000?005fff 02000?02fff sa2 0 0 0 0 0 0 1 1 8/4 006000?007fff 03000?03fff sa3 0 0 0 0 01000?11111 96/48 008000?01ffff 04000?0ffff sa4 0 0 0 1 x x x x 128/64 020000?03ffff 10000?1ffff sa5 0 0 1 0 x x x x 128/64 040000?05ffff 20000?2ffff sa6 0 0 1 1 x x x x 128/64 060000?07ffff 30000?3ffff sa7 0 1 0 0 x x x x 128/64 080000?09ffff 40000?4ffff sa8 0 1 0 1 x x x x 128/64 0a0000?0bffff 50000?5ffff sa9 0 1 1 0 x x x x 128/64 0c0000?0dffff 60000?6ffff sa10 0 1 1 1 x x x x 128/64 0e0000?0fffff 70000?7ffff sa11 1 0 0 0 x x x x 128/64 100000?11ffff 80000?8ffff sa12 1 0 0 1 x x x x 128/64 120000?13ffff 90000?9ffff sa13 1 0 1 0 x x x x 128/64 140000?15ffff a0000?affff sa14 1 0 1 1 x x x x 128/64 160000?17ffff b0000?bffff sa15 1 1 0 0 x x x x 128/64 180000?19ffff c0000?cffff sa16 1 1 0 1 x x x x 128/64 1a0000?1bffff d0000?dffff sa17 1 1 1 0 x x x x 128/64 1c0000?1dffff e0000?effff sa18 1 1 1 1 x x x x 128/64 1e0000?1fffff f0000?fffff device sector address a7?a0 sector size (x16) address range (x32) address range am29pl320db 00000000 512 words/256 double words 000000h?0001ffh 00000h?000ffh
14 am29pl320d june 13, 2005 autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. how- ever, the autoselect codes can also be accessed in- system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address input a9. address inputs must be as shown in table 8. in ad- dition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (table 4). table 8 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7-dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 13. this method does not require v id . see ?command definitions? for details on using the autoselect mode. table 8. am29pl320d autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences. see table 13. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. sector protection and unprotection must be imple- mented via programming equipment. the procedure requires high voltage (v id ) to be placed on address input a9 and control input oe#. this method is com- patible with programmer routines written for earlier amd 3.0 volt devices. publication number 24136 con- tains further details; contact an amd representative to request a copy. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. note that after the sector unpro- tect operation, all previously protected sectors must be re-protected using the sector protect algorithm. the device features a temporary unprotect command sequence to allow changing array data in-system. see ?temporary sector unprotect enable/disable command sequence? for more information. description mode ce# oe# we# a19?12 a11?a10 a9 a8?a7 a6 a5?a4 a3 a2 a1 a0 dq31? dq8 dq7?dq0 manufacturer id : amd l l h x x v id xlxxxll x 01h device id read cycle 1 word l l h xxv id xlxlllh 22h 7eh dbl. word l l h 222222h read cycle 2 word l l h xxv id xlxhhhl 22h 03h dbl. word l l h 222222h read cycle 3 word l l h xxv id xlxhhhh 22h 00h (bottom boot) 01h (top boot) dbl. word l l h 222222h secsi ? sector indicator bit llhxxv id xlxllhh x 80h (factory locked) 00h (not factory locked) sector protection verification llhsaxv id xlxllhl x 01h (protected) 00h (unprotected)
june 13, 2005 am29pl320d 15 common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of de- vices. software support can then be device- independent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h in double word mode (or address aah in word mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 9?12. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 9?12. the system must write the reset command to return the de- vice to the autoselect mode. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alterna- tively, contact an amd representative for copies of these documents. table 9. cfi query identification string addresses (double word mode) addresses (word mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
16 am29pl320d june 13, 2005 table 10. system interface string addresses (double word mode) addresses (word mode) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase), d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp input present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp input present) 1fh 3eh 0004h typical timeout per single word/double word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for word/ double word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0006h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) table 11. device geometry definition addresses (double word mode) addresses (word mode) data description 27h 4eh 0016h device size = 2 n byte 28h 29h 50h 52h 0005h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 58h 0004h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0000h 0000h 0080h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0040h 0000h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0003h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 000eh 0000h 0000h 0004h erase block region 4 information
june 13, 2005 am29pl320d 17 secsi ? (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is a minimum of 128 words (64 double words) in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. current version of de- vice has 512 words; future versions will have only 128 words. this should be considered during sys- tem design. amd offers the device with the secsi sector either factory locked or customer lockable. the factory- locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sec- tor indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secsi sector unprotected, allowing customers to utilize the that sector in any manner they choose. the customer- lockable version has the secsi (secured silicon) sec- tor indicator bit permanently set to a ?0.? thus, the secsi sector indicator bit prevents customer-lockable table 12. primary vendor-specific extended query addresses (double word mode) addresses (word mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0032h minor version number, ascii 45h 8ah 0000h address sensitive unlock 0 = required, 1 = not required 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0001h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800a mode 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = 4 word linear burst, 02 = 8 word linear burst, 03 = 32 linear burst, 04 = 4 word interleave burst 4ch 98h 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7?d4: volt; d3?d0: 100 millivolt. 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7?d4: volt; d3?d0: 100 millivolt. 50h a0h 0000h program suspend 00h = not supported, 01h = supported
18 am29pl320d june 13, 2005 devices from being used to replace devices that are factory locked. the system accesses the secsi sector through a command sequence (see ?enter secsi ? sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up the device reverts to sending commands to the boot sec- tors. factory locked: secsi sector programmed and protected at the factory in a factory locked device, the secsi sector is pro- tected when the device is shipped from the factory. the secsi sector cannot be modified in any way. the device is available preprogrammed with one of the fol- lowing: a random, secure esn only customer code through the expressflash service both a random, secure esn and customer code through the expressflash service. in devices that have an esn, a bottom boot device will have the 8-word (4-double word) esn in the lowest ad- dressable memory area at addresses 000000h? 000003h in double word mode (or 000000h?000007h in word mode). in the top boot device the starting ad- dress of the esn will be at the bottom of the lowest 8 kbyte boot sector at addresses 1f8000h?1f8003h in double word mode (or addresses fc0000h?fc0007h in word mode). customers may opt to have their code programmed by amd through the amd expressflash service. amd programs the customer?s code, with or without the ran- dom esn. the devices are then shipped from amd?s factory with the secsi sector permanently locked. contact an amd representative for details on using amd?s expressflash service. customer lockable: secsi sector not programmed or locked at the factory if the security feature is not required, the secsi sector can be treated as an additional flash memory space, expanding the size of the available flash array. cur- rent version of device has 512 words; future ver- sions will have only 128 words. this should be considered during system design. the secsi sec- tor can be read, programmed, and erased as often as required. ( in upcoming versions of this device, the secsi sector erase function will not be available. ) note that the accelerated programming (acc) and unlock bypass functions are not available when programming the secsi sector. the secsi sector can be locked in-system by perform- ing the following steps: write the three-cycle enter secsi sector region command sequence. write 60h to any address (protect command). wait 150 s, and then write 40h to address 01h (ver- ify command). read from address 02h. the data should be 01h. write the reset command (f0h to any address). write the four-cycle exit secsi sector command se- quence to return to reading from the array. to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 1. the secsi sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. figure 1. secsi sector protect verify write protect (wp#) the write protect function provides a hardware method of protecting certain boot sectors without using v id . if the system asserts v il on the wp# input, the device disables program and erase functions in sector 0 (for bottom boot) or sector 18 (for top boot) independently of whether those sectors were protected or unpro- write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
june 13, 2005 am29pl320d 19 tected using the method described in ?sector protec- tion/unprotection?. if the system asserts v ih on the wp# input, the device reverts to whether sector 0 or 18 was last set to be protected or unprotected. that is, sector protection or unprotection for that sector depends on whether they were last protected or unprotected using the method described in ?sector protection/unprotection?. note that the wp# input must not be left floating or un- connected; inconsistent behavior of the device may re- sult. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 13 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must pro- vide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to reading array data on power-up. command definitions writing specific address and data commands or se- quences into the command register initiates device operations. table 13 defines the valid register com- mand sequences. note that writing incorrect address and data values or writing them in the improper se- quence may place the device in an unknown state. a reset command is required to return the device to nor- mal operation . all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ?ac characteristics? section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or em- bedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more infor- mation on this mode. the system must issue the reset command to re-en- able the device for reading array data if dq5 goes high, or while in the autoselect mode. see the ?reset command? section, next. see also ?requirements for reading array data? in the ?device bus operations? section for more information. the read operations table provides the read parame- ters, and figure 13 shows the timing diagram. reset command writing the reset command to the device resets the de- vice to reading array data. address bits are don?t care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete.
20 am29pl320d june 13, 2005 the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 13 shows the address and data requirements. the autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read any number of autoselect codes without reinitiating the command sequence. tables 13 and 14 show the address and data require- ments for the command sequence. to determine sec- tor protection information, the system must write to the appropriate sector address (sa). tables 4 and 6 show the address range associated with each sector. the system must write the reset command to exit the autoselect mode and return to reading array data. enter secsi ? sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing a random, eight-word (or four double word) electronic serial number (esn). the system can ac- cess the secsi sector region by issuing the three- cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sec- tor command sequence. the exit secsi sector com- mand sequence returns the device to normal operation. table 13 shows the address and data re- quirements for both command sequences. see also ?secsi ? (secured silicon) sector flash memory region? for further information. word/double word program command sequence the system may program the device by word or double word, depending on the state of the word# input. programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically gener- ates the program pulses and verifies the programmed cell margin. table 13 shows the address and data re- quirements for the program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. see ?write operation status? for informa- tion on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. the program command sequence should be reinitiated once the de- vice has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1,? or cause the data# polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes or words to the device faster than using the standard program command sequence. the unlock by- pass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the de- vice then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the pro- gram address and data. additional data is programmed in the same manner. this mode dis- penses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 13 shows the re- quirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycles. the device then returns to reading array data. figure 2 illustrates the algorithm for the program oper- ation. see the program/erase operations table in ?ac characteristics? for parameters, and to figure 17 for timing diagrams.
june 13, 2005 am29pl320d 21 note: see table 13 for program command sequence figure 2. program operation start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
22 am29pl320d june 13, 2005 chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 13 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embed- ded erase algorithm are ignored. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase op- eration by using dq7, dq6, or dq2. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 3 illustrates the algorithm for the erase opera- tion. see the program/erase operations tables in ?ac characteristics? for parameters, and to figure 18 for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. table 13 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the in- terrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase sus- pend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector ad- dresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the ?dq3: sector erase timer? section.) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, or dq2. (refer to ?write operation status? for information on these status bits.) figure 3 illustrates the algorithm for the erase opera- tion. refer to the program/erase operations tables in the ?ac characteristics? section for parameters, and to figure 18 for timing diagrams. erase suspend/erase resume commands the erase suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algo- rithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. ad- dresses are ?don?t-cares? when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maxi- mum of 20 s to suspend the erase operation. however, when the erase suspend command is writ- ten during the sector erase time-out, the device immediately terminates the time-out period and sus- pends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase
june 13, 2005 am29pl320d 23 suspends? all sectors selected for erasure.) note that unlock bypass programming is not allowed when the device is erase-suspended. reading at any address within erase-suspended sec- tors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. the system can deter- mine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see ?autoselect command sequence? for more information. the system must write the erase resume command (address bits are ?don?t care?) to exit the erase sus- pend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. notes: 1. see table 13 for erase command sequence. 2. see ?dq3: sector erase timer? for more information. figure 3. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
24 am29pl320d june 13, 2005 temporary sector unprotect enable/dis- able command sequence the temporary unprotect command sequence is a four-bus-cycle operation. the sequence is initiated by writing two unlock write cycles. a third write cycle sets up the command. the fourth and final write cycle en- ables or disables the temporary unprotect feature. if the temporary unprotect feature is enabled, all sectors are temporarily unprotected. the system may program or erase data as needed. when the system writes the temporary unprotect disable command sequence, all sectors return to their previous protected or unpro- tected settings. see table 13 and figure 4 for more information. notes: 1. all protected sectors are unprotected. if wp# = v il , the first or last 64 kbyte sector will remain protected. 2. all previously protected sectors are protected once again. figure 4. temporary sector unprotect algorithm start write temporary sector unprotect enable command sequence write temporary sector unprotect disable command sequence perform erase or program operations procedure complete (note 1) (note 2)
june 13, 2005 am29pl320d 25 command definitions table 13. command definitions (double word mode) legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a19?a12 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq31?dq8 are don?t cares for unlock and command cycles. 5. address bits a19?a11 are don?t cares for unlock and command cycles, unless sa or pa required. 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 8. the fourth cycle of the autoselect command sequence is a read cycle. 9. dq31?dq16 output 2222h for device id reads. the device id must be read across the fourth, fifth, and sixth cycles. the sixth cycle specifies 22222200h for bottom boot devices and 22222201h for top boot devices. 10. the data is 80h for factory locked and 00h for not factory locked. 11. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. 12. command is valid when device is ready to read array data or when device is in autoselect mode. 13. the unlock bypass command is required prior to the unlock bypass program command. 14. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 15. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 16. the erase resume command is valid only during the erase suspend mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 00 01 device id (note 9) 6 555 aa 2aa 55 555 90 01 227e 0e 2203 0f 2200 2201 secsi ? sector factory protect (note 10) 4 555 aa 2aa 55 (ba) 555 90 (ba) x03 (note 10) sector protect verify (note 11) 4 555 aa 2aa 55 555 90 (sa) x02 (note 11) enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 cfi query (note 12) 1 55 98 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 13) 2 xxx a0 pa pd unlock bypass reset (note 14) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 15) 1 xxx b0 erase resume (note 16) 1 xxx 30 temporary sector unprotect enable 4 555 aa 2aa 55 555 e0 xxx 01 temporary sector unprotect disable 4 555 aa 2aa 55 555 e0 xxx 00
26 am29pl320d june 13, 2005 table 14. command definitions (word mode) legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a19?a12 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq31?dq8 are don?t cares for unlock and command cycles. 5. address bits a19?a11 are don?t cares for unlock and command cycles, unless sa or pa required. 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 8. the fourth cycle of the autoselect command sequence is a read cycle. 9. the device id must be read across the fourth, fifth, and sixth cycles. the sixth cycle specifies 2200h for bottom boot devices and 2201h for top boot devices. 10. the data is 80h for factory locked and 00h for not factory locked. 11. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. 12. command is valid when device is ready to read array data or when device is in autoselect mode. 13. the unlock bypass command is required prior to the unlock bypass program command. 14. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 15. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 16. the erase resume command is valid only during the erase suspend mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 aaa aa 555 55 aaa 90 00 01 device id (note 9) 6 aaa aa 555 55 aaa 90 02 227e 1c 2203 1e 2200 2201 secsi ? sector factory protect (note 10) 4 aaa aa 555 55 (ba) aaa 90 (ba) x06 (note 10) sector protect verify (note 11) 4 aaa aa 555 55 aaa 90 (sa) x04 (note 11) enter secsi sector region 3 aaa aa 555 55 aaa 88 exit secsi sector region 4 aaa aa 555 55 aaa 90 xxx 00 cfi query (note 12) 1 55 98 program 4 aaa aa 555 55 aaa a0 pa pd unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program (note 13) 2 xxx a0 pa pd unlock bypass reset (note 14) 2 xxx 90 xxx 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend (note 15) 1 xxx b0 erase resume (note 16) 1 xxx 30 temporary sector unprotect enable 4 aaa aa 555 55 aaa e0 xxx 01 temporary sector unprotect disable 4 aaa aa 555 55 aaa e0 xxx 00
june 13, 2005 am29pl320d 27 write operation status the device provides several bits to determine the sta- tus of a write operation: dq2, dq3, dq5, dq6, and dq7. table 15 and the following subsections describe the functions of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase com- mand sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to programming during erase suspend. when the em- bedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for ap- proximately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. this is analogous to the complement/true datum out- put described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?complement,? or ?0.? the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the de- vice returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7?dq0 on the following read cycles. this is be- cause dq7 may change asynchronously with dq0? dq6 while output enable (oe#) is asserted low. see figure 18 in the ?ac characteristics? section. table 15 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5 figure 5. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
28 am29pl320d june 13, 2005 dq6: toggle bit toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on ?dq7: data# polling?). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 15 shows the outputs for toggle bit i on dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section ?reading toggle bits dq6/dq2? explains the algorithm. figure 20 in the ?ac character- istics? section shows the toggle bit timing diagrams. figure 21 shows the differences between dq2 and dq6 in graphical form. see also the subsection on ?dq2: toggle bit?. dq2: toggle bit the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 15 to compare outputs for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section ?reading toggle bits dq6/dq2? explains the algorithm. see also the dq6: toggle bit subsection. figure 20 shows the toggle bit timing dia- gram. figure 21 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 for the following discussion. when- ever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 6). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure
june 13, 2005 am29pl320d 29 condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if addi- tional sectors are selected for erasure, the entire time- out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from ?0? to ?1.? the system may ignore dq3 if the system can guarantee that the time between addi- tional sector erase commands will always be less than 50 s. see also the ?write operation status? section. after the sector erase command sequence is written, the system should read the status on dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure the device has accepted the command sequence, and then read dq3. if dq3 is ?1?, the internally controlled erase cycle has begun; all further commands (other than erase suspend) are ignored until the erase operation is com- plete. if dq3 is ?0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 15 shows the outputs for dq3. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 n otes: 1 . read toggle bit twice to determine whether or not it is toggling. see text. 2 . recheck toggle bit because it may stop toggling as dq 5 changes to ?1?. see text. figure 6. toggle bit algorithm (note 1) (notes 1, 2)
30 am29pl320d june 13, 2005 table 15. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?dq5: exceeded timing limits? for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle reading within non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a
june 13, 2005 am29pl320d 31 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . -65c to +150c ambient temperature with power applied. . . . . . . . . . . . . . -65c to +125c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9, oe#, acc (note 2) . . . . . . . . ?0.5 v to +13.0 v all other inputs (note 1) . . . . . . . . . ?0.5 v to +5.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, voltages on inputs or i/os may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/os is v cc + 0.5 v. during voltage transitions i/os may overshoot to v cc + 2.0 v for periods up to 20 ns. 2. minimum dc input voltage on inputs a9, oe#, and acc is ?0.5 v. during voltage transitions, a9 and oe# may overshoot v ss to -2.0 v for periods of up to 20 ns. maximum dc input voltage on input a9, oe#, and acc is +13.0 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the de- vice at these or any other conditions above those indi- cated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rat- ing conditions for extended periods may affect device re- liability. figure 7. maximum negative overshoot waveform figure 8. maximum positive overshoot waveform operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0c to +70c industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c v cc supply voltages v cc for regulated voltage range. . . . . . . 3.0 v to 3.6 v v cc for full voltage range . . . . . . . . . . . . 2.7 v to 3.6 v operating ranges define those limits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
32 am29pl320d june 13, 2005 dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 4 ma/mhz, with oe# at v ih . typical v cc is 3.0 v. 2. maximum i cc specifications are tested with v cc = v cc max. 3. the automatic sleep mode current is dependent on the state of oe#. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. not 100% tested. parameter symbol description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active inter-page read current (notes 1, 2) ce# = v il, oe# = v ih 1 mhz 4 50 ma 10 mhz 40 80 ma i cc2 v cc active write current (notes 2, 4) ce# = v il, oe# = v ih 25 80 ma i cc3 v cc standby current (note 2) ce# = v cc 0.3 v 2 5 a i cc4 automatic sleep mode (notes 2, 3, 6) v ih = v cc 0.3 v; v il = v ss 0.3 v oe# = v ih 15 a oe# = v il 220 i cc5 v cc active intra-page read current (note 2) ce# = v il, oe# = v ih 10 mhz 15 50 ma 33 mhz 50 80 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 2.0 v cc + 0.3 v v hh voltage for accelerated programming on acc 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 0.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 x v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage (note 6) 2.3 2.5 v
june 13, 2005 am29pl320d 33 dc characteristics (continued) zero power flash n ote: addresses are switching at 1 mhz. figure 9. i cc1 current vs. time (showing ac tive and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 20 16 4 0 12345 frequency in mhz supply current in ma n ote: t = 25 c figure 10. typical i cc1 vs. frequency 2.7 v 3.6 v 8 12
34 am29pl320d june 13, 2005 test conditions table 16. test specifications key to switching waveforms 2.7 k c l 6.2 k 3.3 v device under te s t n ote: diodes are in3064 or equivalent figure 11. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 12. input waveforms and measurement levels
june 13, 2005 am29pl320d 35 ac characteristics read operations notes: 1. not 100% tested. 2. see figure 11 and table 16 for test specifications. parameter description test setup speed options unit jedec std 60r 70r, 70 90 t avav t rc read cycle time min 60 70 90 ns t avqv t acc address access time ce#=v il , oe#=v il max 60 70 90 ns t elqv t ce chip enable to output delay oe#=v il max 60 70 90 ns t pac c page access time max 20 25 35 ns t glqv t oe output enable to output valid max 20 25 35 ns t ehqz t df chip enable to output high z max 16 ns t ghqz t df output enable to output high z max 16 ns t oeh output enable hold time (note 1) read 0 ns toggle and data# polling 10 ns t axqx t oh output hold time from addresses, oe# or ce#, whichever occurs first (note 1) min 0 ns
36 am29pl320d june 13, 2005 ac characteristics figure 13. conventional read operations timings note: double word configuration: toggle a2, a1, a0. word configuration: toggle a2, a1, a0, a-1. figure 14. page read timings t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v t df t oh a19 - a3 ce# a 2 - a-1 data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
june 13, 2005 am29pl320d 37 ac characteristics double word/word configuration (word#) parameter description speed options unit jedec std 60r 70r, 70 90 t elfl/ t elfh ce# to word# switching low or high max 5 ns t flqz word# switching low to output high z max 16 ns t fhqv word# switching high to output active min 60 70 90 ns dq31 output data output (dq15?dq0) ce# oe# word# t elfl dq30?dq0 data output (dq30?dq0) dq31/a-1 address input t flqz word# switching from double word to word mode dq15 output data output (dq15?dq0) word# t elfh dq30?dq0 data output (dq30?dq0) dq31/a-1 address input t fhqv word# switching from word to double word mode figure 15. word# timings for read operations note: refer to the erase/program operations table for t as and t ah specifications. figure 16. word# timings for write operations ce# we# word# the falling edge of the last we# signal t hold (t ah ) t set (t as )
38 am29pl320d june 13, 2005 ac characteristics program/erase operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter description speed options unit jedec std 60r 70r, 70 90 t avav t wc write cycle time (note 1) min 60 70 90 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 35 45 45 ns t dvwh t ds data setup time min 30 35 45 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 35 35 ns t whwl t wph write pulse width high min 25 30 30 ns t whwh1 t whwh1 programming operation (note 2) word typ 14.3 s double word ty p 1 8 . 3 t whwh2 t whwh2 sector erase operation (note 2) typ 5 sec t vcs v cc setup time (note 1) min 50 s
june 13, 2005 am29pl320d 39 ac characteristics notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 17. program operation timings oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) t ch pa
40 am29pl320d june 13, 2005 ac characteristics notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?). 2. illustration shows device in word mode. figure 18. ac waveforms for chip/sector erase operations note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle figure 19. data# polling timings (during embedded algorithms) oe# ce# addresses v cc we# data 2aah sa t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data we# ce# oe# high z t oe high z dq7 dq6?dq0 complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc
june 13, 2005 am29pl320d 41 ac characteristics note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 20. toggle bit timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va n ote: the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an e rase-suspended sector. figure 21. dq2 vs. dq6 for erase and erase suspend operations enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
42 am29pl320d june 13, 2005 ac characteristics alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter description speed options unit jedec std 60r 70r, 70 90 t avav t wc write cycle time (note 1) min 60 70 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 35 45 45 ns t dveh t ds data setup time min 30 35 45 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 30 35 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) word typ 14.3 s double word ty p 1 8 . 3 t whwh2 t whwh2 sector erase operation (note 2) typ 5 sec
june 13, 2005 am29pl320d 43 ac characteristics notes: 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last two bus cycles of the command sequence. 3. word mode address used as an example. t ghel t ws oe# ce# we# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t whwh1 or 2 t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase figure 22. alternate ce# controlled write operation timings
44 am29pl320d june 13, 2005 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 13 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics includes all inputs except v cc . test conditions: v cc = 3.0 v, one input at a time. data retention * for reference only. bsc is an ansi standard for basic space centering. bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time, 96 and 128 kbyte sector 260 s excludes 00h programming prior to erasure (note 4) sector erase time, 8 and 16 kbyte sector 0.5 60 chip erase time 33.5 s word programming time 14.3 300 s excludes system level overhead (note 5) double word programming time 18.3 360 s chip programming time (note 3) word mode 28 84 s double word mode 18 54 s description min max input voltage with respect to v ss on all inputs except i/o inputs (including a9 and oe#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o inputs ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter test conditions min unit minimum pattern data retention time 150 c 10 years 125 c 20 years parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4.2 5.0 pf c out output capacitance v out = 0 5.4 6.5 pf c in2 control pin capacitance v in = 0 3.9 4.7 pf
june 13, 2005 am29pl320d 45 physical dimensions fbf084?84-ball fine pitch ball grid array (fbga) 11 x 12 mm dwg. rev. ab-01; 7/00
46 am29pl320d june 13, 2005 revision summary revision a (march 7, 2001) initial release. revision b (june 12, 2001) global added 70r speed option. changed data sheet status from advance information to preliminary. distinctive characteristics secsi sector: added note to future compatibility. power consumption: replaced stated maximum val- ues with typical values. general description added section on secsi sector. secsi ? (secured silicon) sector flash memory region added note to indicate sector size and erase function- ality for future devices. dc characteristics added typical values for i cc1 ?i cc5 to table. corrected v in test condition specification to v cc . figure 10, typical i cc1 vs. frequency changed scale on y-axis to 4 ma divisions. revision b+1 (august 30, 2001) autoselect command sequence modified section to point to appropriate tables for au- toselect functions. accelerated program operation specified a voltage range for v hh . table 13, command definitions corrected the autoselect device id command se- quence. the device id is read in cycles 4, 5, and 6 of a single command sequence, not as three separate command sequences as previously shown. separated the word and double word command sequences into two tables for easier reference. dc characteristics added v hh parameter to table. revision c (october 22, 2002) global deleted preliminary status from data sheet. distinctive characteristics clarified endurance specification from ?write cycles? to ?erase cycles.? secsi ? (secured silicon) sector flash memory region added text and figure on secsi sector protect verify function. command definitions modified first paragraph to indicate device behavior when incorrect data or commands are written. dc characteristics changed v il maximum specification. changed v cc test condition for v id parameter. bga ball capacitance added table. revision c+1 (july 21, 2003) common flash interface (cfi) changed url for cfi publications. command definitions added the phrase ?in the improper sequence? to cau- tionary text in first paragraph. erase and programming performance changed typical sector erase time and typical chip erase time. added typical and maximum sector erase times pertaining to 8 and 16 kword sectors. revision c+2 (october 2, 2003) erase suspend/erase resume commands modified text to ?note that unlock bypass programming is not allowed when the device is erase-suspended? in the third paragraph. ac characteristics - double word/word configuration (word#) diagram modified all instances of dq14 to dq30, dq7 to dq15, and dq15 to dq31. revision c+3 (june 13, 2005) cover page / title page added spansion eol cover page and added eol disclaimer to title page.
june 13, 2005 am29pl320d 47 trademarks copyright ? 2003 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are r egistered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .

▲Up To Search▲

Price & Availability of P320DT70RI

	To Download P320DT70RI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .